AVR JTAGICE
JTAGICE mkII JTAG Squid to IDE Connector
Synopsis: This tutorial
demonstrates how to connect the bulky Atmel JTAGICE
mkII connector to a Futurlec
ETT ET-AVR Stamp development board’s JTAG
IDE socket. Since the standard connector on
the JTAGICE will cover up the pins needed to
interface any SPI-based peripherals on the
board, using a squid adapter leaves them free
of obstruction so you can use them again and
source level debug SPI protocols at the same
time.
Keywords: Atmel JTAGICE mkII, JTAG squid, JTAG pinout, IDE pinout, Futurlec ETT ET-AVR Stamp, AVR ATMega128, AVR Stamp
I’ve been working with the Futurlec ET-AVR Stamp which is a fantastic $20 ATMega128 based board you can buy with an adjunct ET-AVR Stamp development board. With these components, you can easily have a $50 AVR development system (if you don’t count the JTAGICE.) If you want source level debugging, you need a JTAG programmer and that’s where things got interesting with the Futurlec dev board. The AVR stamp does not have a JTAG connector on the module, so JTAG debugging is done only through the dev board.
This is the Atmel JTAGICE mkII with the bulky, problem connector highlighted:
If you’re not using certain pins on the ATMega128 module, a direct connection of the JTAG connector to the JTAG IDE socket will work just fine. Here’s a shot of how the Atmel JTAGICE mkII connects to the AVR dev board when the SPI pins on the micro are not being used:
No problem. However, once you want to connect a SPI device such as an SD/MMC device, the JTAG connector will no longer physically fit:
Regardless of whether you use the male or female headers on the dev board, the JTAG socket will not fit due to the overlap of the circuit board with the dev board headers as shown above.
The solution: a JTAG squid cable. You can either make one [update 2/17/09 - use this technique] or scrounge one up like I did from my STK500 dev kit from Atmel. Then you have to physically map the squid to the IDE socket on the dev board. The JTAG IDE socket on the dev board looks like this:
Identify Pin 1 on the IDE socket which is on the top right if the socket key is on the top:
The pinout goes 1,3,5,7,9 right to left along the keyed top of the IDE connector and 2,4,6,8,10 right to left along the bottom row opposite the key.
The squid cable header will connect to the JTAGICE mkII. The two pieces are the JTAGICE bulky connector:
Pin 1 is identified:
and the squid socket. You can see the key on both the male and female components.
The pin mapping to the ribbon cable is Pin 1 - black and it goes in sequence to pin 10 which is brown on the ribbon above.
Pin 1 is identified on the JTAG squid IDE connector:
After attaching the squid IDE to the JTAGICE mkII bulky JTAG connector, it’s just a matter of mapping the ribbon leads on the squid to the IDE socket on the dev board. You can use this color coding as a guide to see how they map to the IDE socket in the pictures below:
Pin 1 - black - TCK - output
Pin 2 - white - GND
Pin 3 - gray - TDO - input
Pin 4 - purple - VTref - input
Pin 5 - blue - TMS -output
Pin 6 - green - nSRST - out or in
Pin 7 - yellow - n/a
Pin 8 - orange - nTRST - not connected
Pin 9 - red - TDI - output
Pin 10 - brown - GND
The back of the JTAGICE connector has the pin definitions if you need but not the mapping to the IDE ribbon colors:
Here’s how the squid looks from the JTAGICE mkII as it’s mapped into the IDE connector on the dev board:
Summary: The solution to the bulky connector on the JTAGICE mkII is the JTAG squid cable directly mapped to the dev board JTAG IDE socket. With this solution in place, you can debug SPI protocols on the Futurlec AVR stamp board with JTAG and source level debugging.
Keywords: Atmel JTAGICE mkII, JTAG squid, JTAG pinout, IDE pinout, Futurlec ETT ET-AVR Stamp, AVR ATMega128, AVR Stamp
I’ve been working with the Futurlec ET-AVR Stamp which is a fantastic $20 ATMega128 based board you can buy with an adjunct ET-AVR Stamp development board. With these components, you can easily have a $50 AVR development system (if you don’t count the JTAGICE.) If you want source level debugging, you need a JTAG programmer and that’s where things got interesting with the Futurlec dev board. The AVR stamp does not have a JTAG connector on the module, so JTAG debugging is done only through the dev board.
This is the Atmel JTAGICE mkII with the bulky, problem connector highlighted:
If you’re not using certain pins on the ATMega128 module, a direct connection of the JTAG connector to the JTAG IDE socket will work just fine. Here’s a shot of how the Atmel JTAGICE mkII connects to the AVR dev board when the SPI pins on the micro are not being used:
No problem. However, once you want to connect a SPI device such as an SD/MMC device, the JTAG connector will no longer physically fit:
Regardless of whether you use the male or female headers on the dev board, the JTAG socket will not fit due to the overlap of the circuit board with the dev board headers as shown above.
The solution: a JTAG squid cable. You can either make one [update 2/17/09 - use this technique] or scrounge one up like I did from my STK500 dev kit from Atmel. Then you have to physically map the squid to the IDE socket on the dev board. The JTAG IDE socket on the dev board looks like this:
Identify Pin 1 on the IDE socket which is on the top right if the socket key is on the top:
The pinout goes 1,3,5,7,9 right to left along the keyed top of the IDE connector and 2,4,6,8,10 right to left along the bottom row opposite the key.
The squid cable header will connect to the JTAGICE mkII. The two pieces are the JTAGICE bulky connector:
Pin 1 is identified:
and the squid socket. You can see the key on both the male and female components.
The pin mapping to the ribbon cable is Pin 1 - black and it goes in sequence to pin 10 which is brown on the ribbon above.
Pin 1 is identified on the JTAG squid IDE connector:
After attaching the squid IDE to the JTAGICE mkII bulky JTAG connector, it’s just a matter of mapping the ribbon leads on the squid to the IDE socket on the dev board. You can use this color coding as a guide to see how they map to the IDE socket in the pictures below:
Pin 1 - black - TCK - output
Pin 2 - white - GND
Pin 3 - gray - TDO - input
Pin 4 - purple - VTref - input
Pin 5 - blue - TMS -output
Pin 6 - green - nSRST - out or in
Pin 7 - yellow - n/a
Pin 8 - orange - nTRST - not connected
Pin 9 - red - TDI - output
Pin 10 - brown - GND
The back of the JTAGICE connector has the pin definitions if you need but not the mapping to the IDE ribbon colors:
Here’s how the squid looks from the JTAGICE mkII as it’s mapped into the IDE connector on the dev board:
Summary: The solution to the bulky connector on the JTAGICE mkII is the JTAG squid cable directly mapped to the dev board JTAG IDE socket. With this solution in place, you can debug SPI protocols on the Futurlec AVR stamp board with JTAG and source level debugging.
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